View AD7890ACHIPS-2_3973685.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7890 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 functional block diagram features fast 12-bit adc with 5.9 s conversion time eight single-ended analog input channels selection of input ranges: 10 v for ad7890-10 0 v to 4.096 v for ad7890-4 0 v to 2.5 v for ad7890-2 allows separate access to multiplexer and adc on-chip track/hold amplifier on-chip reference high-speed, flexible, serial interface single supply, low-power operation (50 mw max) power-down mode (75 w typ) functional block diagram track/hold 2k ad7890 c ext convst v dd mux out sha in ref out/ ref in agnd agnd dgnd sclk tfs rfs data out data in smode v in8 v in7 v in6 v in5 v in4 v in3 v in2 v in1 clk in signal scaling * signal scaling * signal scaling * signal scaling * signal scaling * signal scaling * signal scaling * signal scaling * * no scaling on ad7890-2 clock output/control register 12-bit adc mux 2.5v reference power dissipation in normal mode is low at 30 mw typ and the part can be placed in a standby (power-down) mode if it is not required to perform conversions. the ad7890 is fabricated in analog devices linear compatible cmos (lc 2 mos) process, a mixed technology process that combines precision bipolar circuits with low power cmos logic. the part is available in a 24-lead, 0.3" wide, plastic or hermetic dual-in-line package or in a 24-lead small outline package (soic). product highlights 1. complete 12-bit data acquisition system-on-a-chip the ad7890 is a complete monolithic adc combining an eight-channel multiplexer, 12-bit adc, 2.5 v reference and a track/hold amplifier on a single chip. 2. separate access to multiplexer and adc the ad7890 provides access to the output of the multiplexer allowing one antialiasing filter for eight channelsa consid- erable saving over the eight antialiasing filters required if the multiplexer was internally connected to the adc. 3. high-speed serial interface the part provides a high-speed serial interface for easy con- nection to serial ports of microcontrollers and dsp processors. general description the ad7890 is an eight-channel 12-bit data acquisition system. the part contains an input multiplexer, an on-chip track/hold amplifier, a high-speed 12-bit adc, a 2.5 v reference and a high speed, serial interface. the part operates from a single 5 v supply and accepts an analog input range of 10 v (ad7890-10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the multiplexer on the part is independently accessible. this allows the user to insert an antialiasing filter or signal conditioning, if required, between the multiplexer and the adc. this means that one antialiasing filter can be used for all eight channels. connection of an external capacitor allows the user to adjust the time given to the multiplexer settling to include any external delays in the filter or signal conditioning circuitry. output data from the ad7890 is provided via a high-speed bidirectional serial interface port. the part contains an on-chip control register, allowing control of channel selection, conver- sion start and power-down via the serial port. versatile, high speed logic ensures easy interfacing to serial ports on microcon- trollers and digital signal processors. in addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the ad7890 is also speci- fied for dynamic performance parameters including harmonic distortion and signal-to-noise ratio. lc 2 mos 8-channel, 12-bit serial, data acquisition system
rev. b C2C ad7890?pecifications parameter a versions 1 b versions s version unit test conditions/comments dynamic performance using external convst . any channel signal to (noise + distortion) ratio 2 70 70 70 db min f in = 10 khz sine wave, f sample = 100 khz 3 total harmonic distortion (thd) 2 C78 C78 C78 db max f in = 10 khz sine wave, f sample = 100 khz 3 peak harmonic or spurious noise 2 C79 C79 C79 db max f in = 10 khz sine wave, f sample = 100 khz 3 intermodulation distortion fa = 9 khz, fb = 9.5 khz, f sample = 100 khz 3 2nd order terms C80 C80 C80 db typ 3rd order terms C80 C80 C80 db typ channel-to-channel isolation 2 C80 C80 C80 db max f in = 1 khz sine wave dc accuracy resolution 12 12 12 bits minimum resolution for which no missing codes are guaranteed 12 12 12 bits relative accuracy 2 1 0.5 1 lsb max differential nonlinearity 2 1 1 1 lsb max positive full-scale error 2 2.5 2.5 2.5 lsb max full-scale error match 4 2 2 2 lsb max ad7890-2, ad7890-4 unipolar offset error 2 2 2 2 lsb max unipolar offset error match 2 2 2 lsb max ad7890-10 only negative full-scale error 2 2 2 2 lsb max bipolar zero error 2 5 5 5 lsb max bipolar zero error match 2 2 2 lsb max analog inputs ad7890-10 input voltage range 10 10 10 volts input resistance 20 20 20 k ? min ad7890-4 input voltage range 0 to 4.096 0 to 4.096 0 to 4.096 volts input resistance 11 11 11 k ? min ad7890-2 input voltage range 0 to 2.5 0 to 2.5 0 to 2.5 volts input current 50 50 200 na max mux out output output voltage range 0 to 2.5 0 to 2.5 0 to 2.5 volts output resistance (ad7890-10, ad7890-4) 3/5 3/5 3/5 k ? min/k ? max (ad7890-2) 222k ? max assuming v in is driven from low impedance sha in input input voltage range 0 to 2.5 0 to 2.5 0 to 2.5 volts input current 50 50 50 na max reference output/input ref in input voltage range 2.375/2.625 2.375/2.625 2.375/2.625 v min/v max 2.5 v 5% input impedance 1.6 1.6 1.6 k ? min resistor connected to internal reference node input capacitance 5 10 10 10 pf max ref out output voltage 2.5 2.5 2.5 v nom ref out error @ 25 c 10 10 10 mv max t min to t max 20 20 25 mv max ref out temperature coefficient 25 25 25 ppm/ c typ ref out output impedance 222k ? nom logic inputs input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 a max v in = 0 v to v dd input capacitance, c in 5 10 10 10 pf max (v dd = 5 v, agnd = dgnd = 0 v, ref in = 2.5 v, f clk in = 2.5 mhz external, mux out connect to sha in. all specifications t min to t max unless otherwise noted.)
rev. b C3C ad7890 absolute maximum ratings * (t a = 25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v analog input voltage to agnd ad7890-10, ad7890-4 . . . . . . . . . . . . . . . . . . . . . . . 17 v ad7890-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . C5 v, +10 v reference input voltage to agnd . . . C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . C0.3 v to v dd + 0.3 v digital output voltage to dgnd . . . . C0.3 v to v dd + 0.3 v operating temperature range commercial (a, b versions) . . . . . . . . . . . C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c plastic dip package, power dissipation . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . 105 c/w lead temperature (soldering, 10 sec) . . . . . . . . . . . . 260 c cerdip package, power dissipation . . . . . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 70 c/w lead temperature (soldering, 10 sec) . . . . . . . . . . . . 300 c soic package, power dissipation . . . . . . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature linearity package model range error option * ad7890an-2 C40 c to +85 c 1 lsb n-24 ad7890bn-2 C40 c to +85 c 1/2 lsb n-24 ad7890ar-2 C40 c to +85 c 1 lsb r-24 ad7890br-2 C40 c to +85 c 1/2 lsb r-24 ad7890sq-2 C55 c to +125 c 1 lsb q-24 ad7890an-4 C40 c to +85 c 1 lsb n-24 ad7890bn-4 C40 c to +85 c 1/2 lsb n-24 ad7890ar-4 C40 c to +85 c 1 lsb r-24 ad7890br-4 C40 c to +85 c 1/2 lsb r-24 ad7890sq-4 C55 c to +125 c 1 lsb q-24 ad7890an-10 C40 c to +85 c 1 lsb n-24 ad7890bn-10 C40 c to +85 c 1/2 lsb n-24 ad7890ar-10 C40 c to +85 c 1 lsb r-24 ad7890br-10 C40 c to +85 c 1/2 lsb r-24 ad7890sq-10 C55 c to +125 c 1 lsb q-24 * n = plastic dip; q = cerdip; r = soic. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7890 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. parameter a versions 1 b versions s version unit test conditions/comments logic outputs output high voltage, v oh 4.0 4.0 4.0 v min i source = 200 a output low voltage, v ol 0.4 0.4 0.4 v max i sink = 1.6 ma serial data output coding ad7890-10 twos complement ad7890-4 straight (natural) binary ad7890-2 straight (natural) binary conversion rate conversion time 5.9 5.9 5.9 s max f clk in = 2.5 mhz, mux out connected to sha in track/hold acquisition time 2, 5 222 s max power requirements v dd 555v nom 5% for specified performance i dd (normal mode) 10 10 10 ma max logic inputs = 0 v or v dd i dd (standby mode) 6 @ 25 c151515 a typ logic inputs = 0 v or v dd power dissipation normal mode 50 50 50 mw max typically 30 mw standby mode @ 25 c 757575 w typ notes 1 temperature ranges are as follows: a, b versions: C40 c to +85 c; s version: C55 c to +125 c. 2 see terminology. 3 this sample rate is only achievable when tiling the part in external clocking mode. 4 full-scale error match applies to positive full scale for the ad7890-2 and ad7890-4. it applies to both positive and negative f ull scale for the ad7890-10. 5 sample tested @ 25 c to ensure compliance. 6 analog inputs on ad7890-10 must be at 0 v to achieve correct power-down current. specifications subject to change without notice. warning! esd sensitive device
rev. b ad7890 C4C timing characteristics 1, 2 limit at t min , t max parameter (a, b, s versions) unit conditions/comments f clkin 3 100 khz min master clock frequency. for specified performance 2.5 mhz max t clk in lo 0.3 t clk in ns min master clock input low time t clk in hi 0 3 t clk in ns min master clock input high time tr 4 25 ns max digital output rise time. typically 10 ns tf 4 25 ns max digital output fall time. typically 10 ns t convert 5.9 s max conversion time t cst 100 ns min convst pulsewidth self-clocking mode t 1 t clk in hi + 50 ns max rfs low to sclk falling edge t 2 5 25 ns max rfs low to data valid delay t 3 t clk in hi ns nom sclk high pulsewidth t 4 t clk in lo ns nom sclk low pulsewidth t 5 5 20 ns max sclk rising edge to data valid delay t 6 40 ns max sclk rising edge to rfs delay t 7 6 50 ns max bus relinquish time after rising edge of sclk t 8 0 ns min tfs low to sclk falling edge t clk in + 50 ns max t 9 0 ns min data valid to tfs falling edge setup time (a2 address bit) t 10 20 ns min data valid to sclk falling edge setup time t 11 10 ns min data valid to sclk falling edge hold time t 12 20 ns min tfs to sclk falling edge hold time external-clocking mode t 13 20 ns min rfs low to sclk falling edge setup time t 14 5 40 ns max rfs low to data valid delay t 15 50 ns min sclk high pulsewidth t 16 50 ns min sclk low pulsewidth t 17 5 35 ns max sclk rising edge to data valid delay t 18 20 ns min rfs to sclk falling edge hold time t 19 6 50 ns max bus relinquish time after rising edge of rfs t 19a 6 90 ns max bus relinquish time after rising edge of sclk t 20 20 ns min tfs low to sclk falling edge setup time t 21 10 ns min data valid to sclk falling edge setup time t 22 15 ns min data valid to sclk falling edge hold time t 23 40 ns min tfs to sclk falling edge hold time notes 1 sample tested at C25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 see figures 8 to 11. 3 the ad7890 is production tested with f clk in at 2.5 mhz. it is guaranteed by characterization to operate at 100 khz. 4 specified using 10% and 90% points on waveform of interest. 5 these numbers are measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.4 v. 6 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figur e 1. the measured number is then extrapolated back to remove effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the tim ing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. to output pin +2.1v 1.6ma 200 a 50pf figure 1. load circuit for access time and bus relinquish time (v dd = 5 v 5%, agnd = dgnd = 0 v, ref in = 2.5 v, f clk in = 2.5 mhz external, mux out connected to sha in.)
rev. b ad7890 C5C pin function descriptions pin mnemonic description 1 agnd analog ground. ground reference for track/hold, comparator and dac. 2 smode control input. determines whether the part operates in its external clocking (slave) or self-clocking (master) serial mode. with smode at a logic low, the part is in its self-clocking serial mode with rfs and sclk as outputs. this self-clocking mode is useful for connection to shift registers or to serial ports of dsp processors. with smode at a logic high, the part is in its external clocking serial mode with sclk and rfs as inputs. this external clocking mode is useful for connection to the serial port of microcontrollers such as the 8xc51 and the 68hcxx and for connection to the serial ports of dsp processors. 3 dgnd digital ground. ground reference for digital circuitry. 4c ext external capacitor. an external capacitor is connected to this pin to determine the length of the internal pulse (see convst input and control register section). larger capacitances on this pin extend the pulse to allow for settling time delays through an external antialiasing filter or signal conditioning circuitry. 5 convst convert start. edge-triggered logic input. a low to high transition on this input puts the track/hold into hold and initiates conversion provided that the internal pulse has timed out (see control register section). if the internal pulse is active when the convst goes high, the track/hold will not go into hold until the pulse times out. if the internal pulse has timed out when convst g oes high, the rising edge of convst drives the track/hold into hold and initiates conversion. 6 clk in clock input. an external ttl-compatible clock is applied to this input pin to provide the clock source for the conversion sequence. in the self-clocking serial mode, the sclk output is derived from this clk in pin. 7 sclk serial clock input. in the external clocking (slave) mode (see serial interface section) this is an externally applied serial clock which is used to load serial data to the control register and to access data from the output register. in the self-clocking (master) mode, the internal serial clock, which is derived from the clock input (clk in), appears on this pin. once again, it is used to load serial data to the control register and to access data from the output register. 8 tfs transmit frame synchronization pulse. active low logic input with serial data expected after the falling edge of this signal. 9 rfs receive frame synchronization pulse. in the external clocking mode, this pin is an active low logic input with rfs provided externally as a strobe or framing pulse to access serial data from the output register. in the s elf-clocking mode, it is an active low output which is internally gen erated and provides a strobe or framing pulse for serial data from the output register. for applications which require that data be transmitted and received at the same time, rfs and tfs should be connected together. 10 data out serial data output. sixteen bits of serial data are provided with one leading zero, preceding the three address bits of the control register and the 12 bits of conversion data. serial data is valid on the falling edge of sclk for sixteen edges after rfs goes low. output coding from the adc is twos complement for the ad7890-10 and straight binary for the ad7890-4 and ad7890-2. 11 data in serial data input. serial data to be loaded to the control register is provided at this input. the first five bits of serial data are loaded to the control register on the first five falling edges of sclk after tfs goes low. serial data on subsequent sclk edges is ignored while tfs remains low. 12 v dd positive supply voltage, 5 v 5%. 13 mux out multiplexer output. the output of the multiplexer appears at this pin. the output voltage range from this output is 0 v to 2.5 v for the nominal analog input range to the selected channel. the output impedance of this output is nominally 3.5 k ? . if no external antialiasing filter is required, mux out should be connected to sha in. 14 sha in track/hold input. the input to the on-chip track/hold is applied to this pin. it is a high impedance input and the input voltage range is 0 v to 2.5 v. 15 agnd analog ground. ground reference for track/hold, comparator and dac. 16 v in1 analog input channel 1. single-ended analog input. the analog input range on is 10 v (ad7890-10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the channel to be converted is selected using the a0, a1 and a2 bits in the control register. the multiplexer has guaranteed break- before- make operation.
rev. b ad7890 C6C pin mnemonic description 17 v in2 analog input channel 2. single-ended analog input. the analog input range on is 10 v (ad7890- 10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the channel to be converted is selected using the a0, a1 and a2 bits in the control register. the multiplexer has guaranteed break- before-make operation. 18 v in3 analog input channel 3. single-ended analog input. the analog input range on is 10 v (ad7890- 10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the channel to be converted is selected using the a0, a1 and a2 bits in the control register. the multiplexer has guaranteed break- before-make operation. 19 v in4 analog input channel 4. single-ended analog input. the analog input range on is 10 v (ad7890- 10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the channel to be converted is selected using the a0, a1 and a2 bits in the control register. the multiplexer has guaranteed break- before-make operation. 20 v in5 analog input channel 5. single-ended analog input. the analog input range on is 10 v (ad7890- 10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the channel to be converted is selected using the a0, a1 and a2 bits in the control register. the multiplexer has guaranteed break- before-make operation. 21 v in6 analog input channel 6. single-ended analog input. the analog input range on is 10 v (ad7890- 10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the channel to be converted is selected using the a0, a1 and a2 bits in the control register. the multiplexer has guaranteed break- before-make operation. 22 v in7 analog input channel 7. single-ended analog input. the analog input range on is 10 v (ad7890- 10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the channel to be converted is selected using the a0, a1 and a2 bits in the control register. the multiplexer has guaranteed break- before-make operation. 23 v in8 analog input channel 8. single-ended analog input. the analog input range on is 10 v (ad7890- 10), 0 v to 4.096 v (ad7890-4) and 0 v to 2.5 v (ad7890-2). the channel to be converted is selected using the a0, a1 and a2 bits in the control register. the multiplexer has guaranteed break- before-make operation. 24 ref out/ref in voltage reference output/input. the part can be used with either its own internal reference or with an external reference source. the on-chip 2.5 v reference voltage is provided at this pin. when using this internal reference as the reference source for the part, ref out should decoupled to agnd with a 0.1 f disc ceramic capacitor. the output impedance of this reference source is typically 2 k ? . when using an external reference source as the reference voltage for the part, the reference source should be connected to this pin. this overdrives the internal reference and provides the refer- ence source for the part. the ref in input is buffered on-chip. the nominal reference voltage for correct operation of the ad7890 is 2.5 v. pin configuration dip and soic top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7890 agnd ref out/ref in smode v in8 dgnd v in7 c ext v in6 convst v in5 clk in v in4 sclk v in3 tfs v in2 rfs v in1 data out agnd data in sha in v dd mux out
rev. b ad7890 C7C terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan- tization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to (noise + distortion) = (6.02n + 1.76) db thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7890, it is defined as: where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the ad7890 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second and third order terms are of differ- ent significance. the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified sepa- rately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale 1 khz signal to any one of the other seven inputs and determining how much that signal is attenuated in the channel of interest. the figure given is the worst case across all eight channels. relative accuracy relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. positive full-scale error (ad7890-10) this is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal (4 ref in C 1 lsb) after the bipolar zero error has been adjusted out. positive full-scale error (ad7890-4) this is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal (1.638 ref in C 1 lsb) after the unipolar offset error has been adjusted out. positive full-scale error (ad7890-2) this is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal (ref in C 1 lsb) after the unipolar offset error has been adjusted out. bipolar zero error (ad7890-10) this is the deviation of the midscale transition (all 0s to all 1s) from the ideal 0 v (agnd). unipolar offset error (ad7890-2, ad7890-4) this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal 0 v (agnd). negative full-scale error (ad7890-10) this is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal (C4 ref in + 1 lsb) after bipolar zero error has been adjusted out. track/hold acquisition time track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion (the point at which the track/hold returns to track mode). it also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected v in input of the ad7890. it means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a channel change/step input change to v in before starting another conversion, to ensure that the part oper- ates to specification.
rev. b ad7890 C8C control register the control register for the ad7890 contains 5 bits of informa- tion as described below. six serial clock pulses must be provided to the part in order to write data to the control register (seven if the write is required to put the part in standby mode). if tfs returns high before six serial clock cycles then no data transfer takes place to the control register and the write cycle will have to be restarted to write the data to the control register. if, however, the conv bit of the register (see below) is set to a logic 1, then a conversion will be initiated whenever a control register write takes place regardless of how many serial clock cycles the tfs remains low for. the default (power-on) condi- tion of all bits in the control register is 0. msb a2 a1 a0 conv stby a2 address input. this input is the most significant address input for multiplexer channel selection. a1 address input. this is the 2nd most significant address input for multiplexer channel selection. a0 address input. least significant address input for multiplexer channel selection. when the address is written to the control register, an internal pulse is initiated, the pulsewidth of which is determined by the value of capacitance on the c ext pin. when this pulse is active, it ensures the conversion process can- not be activated. this allows for the multiplexer settling time and track/hold acquisition time before the track/hold goes into hold and conversion is initi- ated. in applications where there is an anti-aliasing filter between mux out and sha in, the filter settling time can be taken into account before the input at sha in is sampled. when the internal pulse times out, the track/hold goes into hold and conver- sion is initiated. conv conversion start. writing a 1 to this bit initiates a conversion in a similar manner to the convst input. continuous conversion starts do not take place when there is a 1 in this location. the internal pulse and the conversion process are initiated after the sixth serial clock cycle of the write operation if a 1 is written to this bit. with a 1 in this bit, the hardware conver- sion start i.e., the convst input, is disabled. writing a 0 to this bit enables the hardware convst input. stby standby mode input. writing a 1 to this bit places the device in its standby or power-down mode. writ- ing a 0 to this bit places the device in its normal operating mode. the part does not enter its standby mode until the seventh falling edge of sclk in a write operation. therefore, the part requires seven serial clock pulses in its serial write operation if it is required to put the part into standby. converter details the ad7890 is an eight-channel, 12-bit, single supply, serial data acquisition system. it provides the user with signal scaling, multiplexer, track/hold, reference, a/d converter and versatile serial logic functions on a single chip. the signal scaling allows the part to handle 10 v input signals (ad7890-10) and 0 v to 4.096 v input signals (ad7890-4) while operating from a single 5 v supply. the ad7890-2 contains no signal scaling and accepts an analog input range of 0 v to 2.5 v. the part operates from a 2.5 v reference which can be provided from the parts own internal reference or from an external reference source. unlike other single chip data acquisition solutions, the ad7890 provides the user with separate access to the multiplexer and the a/d converter. this means that the flexibility of separate multi- plexer and adc solutions is not sacrificed with the one-chip solution. with access to the multiplexer output, the user can implement external signal conditioning between the multiplexer and the track/hold. it means that one antialiasing filter can be used on the output of the multiplexer to provide the antialiasing function for all eight channels. conversion is initiated on the ad7890 either by pulsing the convst input or by writing a logic 1 to the conv bit of the control register. when using the hardware convst input, on the rising edge of the convst signal, the on-chip track/hold goes from track to hold mode and the conversion sequence is started provided the internal pulse has timed out. this internal pulse (which appears at the c ext pin) is initiated whenever the multiplexer address is loaded to the ad7890 control register. this pulse goes from high to low when a serial write to the part is initiated. it starts to discharge on the sixth falling clock edge of sclk in a serial write operation to the part. the track/hold cannot go into hold and conversion cannot be initiated until the c ext pin has crossed its trigger point of 2.5 v. the discharge time of the voltage on c ext depends upon the value of capacitor connected to the c ext pin (see c ext functioning section). the fact that the pulse is initiated every time a write to the control register takes place means that the software conversion start and track/hold signal is always delayed by the internal pulse. the conversion clock for the part is generated from the clock signal applied to the clk in pin of the part. conversion time for the ad7890 is 5.9 s from the rising edge of the hardware convst signal and the track/hold acquisition time is 2 s. to obtain optimum performance from the part, the data read operation or control register write operation should not occur during the conversion or during 500 ns prior to the next conver- sion. this allows the part to operate at throughput rates up to 117 khz in the external clocking mode and achieve data sheet specifications. the part can operate at slightly higher throughput rates (up to 127 khz), again in external clocking mode with degraded performance (see timing and control section). the throughput rate for self-clocking mode is limited by the serial clock rate to 78 khz. all unused inputs should be connected to a voltage within the nominal analog input range to avoid noise pickup. on the ad7890-10, if any one of the input channels which are not being converted goes more negative than C12 v, it can interfere with the conversion on the selected channel.
rev. b ad7890 C9C circuit description analog input section the ad7890 is offered as three part types, the ad7890-10 which handles a 10 v input voltage range, the ad7890-4 which handles a 0 v to 4.096 v input range and the ad7890-2 which handles a 0 v to 2.5 v input voltage range. ad7890-10 figure 2 shows the analog input section for the ad7890-10. the analog input range for each of the analog inputs is 10 v into an input resistance of typically 33 k ? . this input is benign with no dynamic charging currents with the resistor attenuator stage followed by the multiplexer and in cases where mux out is connected to sha in this is followed by the high input impedance stage of the track/hold amplifier. the designed code transitions occur on successive integer lsb values (i.e., 1 lsb, 2 lsbs, 3 lsbs...). output coding is twos complement binary with 1 lsb C fs/4096 = 20 v/4096 = 4.88 mv. the ideal input/ output transfer function is shown in table i. 2.5v reference 30k ad7890-10 ref out/ ref in agnd v inx 200 * to adc reference circuitry 7.5k 10k 2k * equivalent on-resistance of multiplexer mux out figure 2. ad7890-10 analog input structure table i. ideal input/output code table for the ad7890-10 digital output analog input 1 code transition +fsr/2 C 1 lsb 2 (9.995117 v) 011 . . . 110 to 011 . . . 111 +fsr/2 C 2 lsbs (9.990234 v) 011 . . . 101 to 011 . . . 110 +fsr/2 C 3 lsbs (9.985352 v) 011 . . . 100 to 011 . . . 101 agnd + 1 lsb (0.004883 v) 000 . . . 000 to 000 . . . 001 agnd (0.000000 v) 111 . . . 111 to 000 . . . 000 agnd C 1 lsb (C0.004883 v) 111 . . . 110 to 111 . . . 111 Cfsr/2 + 3 lsbs (C9.985352 v) 100 . . . 010 to 100 . . . 011 Cfsr/2 + 2 lsbs (C9.990234 v) 100 . . . 001 to 100 . . . 010 Cfsr/2 + 1 lsb (C9.995117 v) 100 . . . 000 to 100 . . . 001 notes 1 fsr is full-scale range and is 20 v with ref in = 2.5 v. 2 1 lsb = fsr/4096 = 4.883 mv with ref in = 2.5 v. ad7890-4 figure 3 shows the analog input section for the ad7890-4. the analog input range for each of the analog inputs is 10 v into an input resistance of typically 15 k ? . this input is benign with no dynamic charging currents with the resistor attenuator stage followed by the multiplexer and in cases where mux out is connected to sha in this is followed by the high input impedance stage of the track/hold amplifier. the designed code transi tions occur on successive integer lsb values (i.e., 1 lsb, 2 lsbs, 3 lsbs . . . ). output coding is straight (natural) binary with 1 lsb = fs/4096 = 4.096 v/4096 = 1 mv. the ideal input/ output transfer function is shown in table ii. 2.5v reference 6k ad7890-4 ref out/ ref in agnd v inx 200 * to adc reference circuitry 9.38k 2k * equivalent on-resistance of multiplexer mux out figure 3. ad7890-4 analog input structure table ii. ideal input/output code table for the ad7890-4 digital output analog input 1 code transition +fsr C 1 lsb 2 (4.095 v) 111 . . . 110 to 111 . . . 111 +fsr C 2 lsbs (4.094 v) 111 . . . 101 to 111 . . . 110 +fsr C 3 lsbs (4.093 v) 111 . . . 100 to 111 . . . 101 agnd + 3 lsbs (0.003 v) 000 . . . 010 to 000 . . . 011 agnd + 2 lsbs (0.002 v) 000 . . . 001 to 000 . . . 010 agnd + 1 lsb (0.001 v) 000 . . . 000 to 000 . . . 001 notes 1 fsr is full-scale range and is 4.096 v with ref in = 2.5 v. 2 1 lsb = fsr/4096 = 1 mv with ref in = 2.5 v. ad7890-2 the analog input section for the ad7890-2 contains no biasing resistors and the selected analog input connects to the multi- plexer and in cases where mux out is connected to sha in this is followed by the high input impedance stage of the track/ hold am plifier. the analog input range is, therefore, 0 v to 2.5 v into a high impedance stage with an input current of less than 50 na. the designed code transitions occur on successive integer lsb values (i.e., l lsb, 2 lsbs, 3 lsbs . . . fs-1 lsbs). out- put coding is straight (natural) binary with 1 lsb = fs/4096 = 2.5 v/4096 = 0.61 mv. the ideal input/output transfer function is shown in table iii. table iii. ideal input/output code table for the ad7890-2 digital output analog input 1 code transition +fsr C 1 lsb 2 (2.499390 v) 111 . . . 110 to 111 . . . 111 +fsr C 2 lsbs (2.498779 v) 111 . . . 101 to 111 . . . 110 +fsr C 3 lsbs (2.498169 v) 111 . . . 100 to 111 . . . 101 agnd + 3 lsbs (0.001831 v) 000 . . . 010 to 010 . . . 011 agnd + 2 lsbs (0.001221 v) 000 . . . 001 to 001 . . . 010 agnd + 1 lsb (0.000610 v) 000 . . . 000 to 000 . . . 001 notes 1 fsr is full-scale range and is 2.5 v with ref in = 2.5 v. 2 1 lsb = fsr/4096 = 0.61 mv with ref in = 2.5 v.
rev. b ad7890 C10C track/hold section the sha in input on the ad7890 connects directly to the input stage of the track/hold amplifier. this is a high impedance input with input leakage currents of less than 50 na. connect- ing the mux out pin directly to the sha in pin connects the multiplexer output directly to the track/hold amplifier. the input voltage range for this input is 0 v to 2.5 v. if external circuitry is connected between mux out and sha in, then the user must ensure that the input voltage range to the sha in input is 0 v to 2.5 v to ensure that the full dynamic range of the converter is utilized. the track/hold amplifier on the ad7890 allows the adc to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. the input bandwidth of the track/hold is greater than the nyquist rate of the adc even when the adc is operated at its maximum throughput rate of 117 khz (i.e., the track/hold can handle input frequencies in excess of 58 khz). the track/hold amplifier acquires an input signal to 12-bit accu- racy in less than 2 s. the operation of the track/hold is essentially transparent to the user. the track/hold amplifier goes from its tracking mode to its hold mode at the start of conversion. the start of conversion is the rising edge of convst (assuming the internal pulse has timed out) for hardware conversion starts and for software conversion starts is the point where the internal pulse is timed out. the aperture time for the track/hold (i.e., the delay time between the external convst signal and the track/hold actually going into hold) is typically 15 ns. for software con- version starts, the time depends on the internal pulsewidths. therefore, for software conversion starts, the sampling instant is not very well defined. for sampling systems which require well defined, equidistant sampling, it may not be possible to achieve optimum performance from the part using the soft- ware conversion start. at the end of conversion, the part returns to its tracking mode. the acquisition time of the track/ hold amplifier begins at this point. reference section the ad7890 contains a single reference pin, labelled ref out/ ref in, which either provides access to the parts own 2.5 v reference or to which an external 2.5 v reference can be con- nected to provide the reference source for the part. the part is specified with a 2.5 v reference voltage. errors in the reference source will result in gain errors in the ad7890s transfer func- tion and will add to the specified full-scale errors on the part. on the ad7893-10, it will also result in an offset error injected in the attenuator stage. the ad7890 contains an on-chip 2.5 v reference. to use this reference as the reference source for the ad7890, simply con- nect a 0.1 f disc ceramic capacitor from the ref out/ref in pin to agnd. the voltage which appears at this pin is inter- nally buffered before being applied to the adc. if this reference is required for use external to the ad7890, it should be buffered as the source impedance of this output is 2 k ? nominal. the tolerance on the internal reference is 10 mv at 25 c with a typical temperature coefficient of 25 ppm/ c and a maximum error over temperature of 25 mv. if the application requires a reference with a tighter tolerance or the ad7890 needs to be used with a system reference, then the user has the option of connecting an external reference to this ref out/ref in pin. the external reference will effectively overdrive the internal reference and thus provide the reference source for the adc. the reference input is buffered but has a nominal 2 k ? resistor connected to the ad7890s internal refer- ence. suitable reference sources for the ad7890 include the ad680, ad780 and ref-43 precision 2.5 v references. timing and control section the ad7890 is capable of two interface modes, selected by the smode input. the first of these is a self-clocking mode where the part provides the frame sync, serial clock and serial data at the end of conversion. in this mode the serial clock rate is determined by the master clock rate of the part (at clk in input). the second mode is an external clocking mode where the user provides the frame sync and serial clock signals to obtain the serial data from the part. in this second mode, the user has control of the serial clock rate up to a maximum of 10 mhz. the two modes are discussed in more detail in the serial interface section. the part also provides hardware and software conversion start features. the former provides a well-defined sampling instant with the track/hold going into hold on the rising edge of the convst signal. for the software conversion start, a write to the conv bit to the control register initiates the conversion sequence. however, for the software conversion start an inter- nal pulse has to time out before the input signal is sampled. this pulse, plus the difficult in maintaining exactly equal delays between each software conversion start command, means that the dynamic performance of the ad7890 may have difficulty meeting spec when used in software conversion start mode. the ad7890 provides separate channel select and conversion start control. this allows the user to optimize the throughput rate of the system. once the track/hold has gone into hold mode, the input channel can be updated and the input voltage can settle to the new value while the present conversion is in progress. assuming the internal pulse has timed out before the convst pulse is exercised, the conversion will consist of 14.5 master clock cycles. in the self-clocking mode, the conversion time is defined as the time from the rising edge of convst to the falling edge of rfs (i.e., when the device starts to transmit its conversion result). this time includes the 14.5 master clock cycles plus the updating of the output register and delay time in outputting the rfs signal, resulting in a total conversion time of 5.9 s maximum. figure 4 shows the conversion timing for the ad890 when used in the self-clocking (master) mode with hardware convst . the timing diagram assumes that the internal pulse is not active when the convst signal goes high. to ensure this, the channel address to be converted should be selected by writing to the control register prior to the convst pulse. sufficient setup time should be allowed between the con- trol register write and the convst to ensure that the internal pulse has timed out. the duration of the internal pulse (and hence the duration of setup time) depends on the value of c ext .
rev. b ad7890 C11C when using the device in the external-clocking mode, the out- put register can be read at any time and the most up-to-date conversion result will be obtained. however, reading data from the output register or writing data to the control register dur- ing conversion or during the 500 ns prior to the next convst will result in reduced performance from the part. a read opera- tion to the output register has most effect on performance with the signal-to-noise ratio likely to degrade especially when higher serial clock rates are used while the code flicker from the part will also increase (see ad7890 performance section). figure 5 shows the timing and control sequence required to obtain optimum performance from the part in the external clocking mode. in the sequence shown, conversion is initiated on the rising edge of convst and new data is available in the output register of the ad7890 5.9 s later. once the read oper- ation has taken place, a further 500 ns should be allowed before track/hold goes into the hold t convert three-state note: (i) signifies an input; (o) signifies an output. pull-up resistor on sclk. data out (o) sclk (o) rfs (o) convst (i) figure 4. self-clocking (master) mode conversion sequence rfs tfs t convert 500ns min convst sclk conversion is initiated and track/hold goes into hold conversion ends 5.9 s later serial read and write operations read and write operations should end 500ns prior to next rising edge of convst next conversion start command figure 5. external clocking (slave) mode timing sequence for optimum performance the next rising edge of convst to optimize the settling of the track/hold before the next conversion is initiated. the diagram shows the read operation and the write operation taking place in parallel. on the sixth falling edge of sclk in the write sequence the internal pulse will be initiated. assuming mux out is connected to sha in, 2 s are required between this sixth falling edge of sclk and the rising edge of convst to allow for the full acquisition time of the track/hold amplifier. with the serial clock rate at its maximum of 10 mhz, the achievable throughput rate for the part is 5.9 s (conversion time) plus 0.6 s (six serial clock pulses before internal pulse is initiated) plus 2 s (acquisition time). this results in a minimum through- put time of 8.5 s (equivalent to a throughput rate of 117 khz). if the part is operated with a slower serial clock, it will impact the achievable throughput rate for optimum performance.
rev. b ad7890 C12C in the self-clocking mode, the ad7890 indicates when conver- sion is complete by bringing the rfs line low and initiating a serial data transfer. in the external clocking mode, there is no indication of when conversion is complete. in many applica- tions, this will not be a problem as the data can be read from the part during conversion or after conversion. however, applications that seek to achieve optimum performance from the ad7890 will have to ensure that the data read does not occur during conversion or during 500 ns prior to the rising edge of convst . this can be achieved in either of two ways. the first is to ensure in software that the read operation is not initiated until 5.9 s after the rising edge of convst . this will only be possible if the software knows when the convst command is issued. the second scheme would be to use the convst signal as both the conversion start signal and an interrupt signal. the simplest way to do this would be to generate a square wave signal for convst with high and low times of 5.9 s (see figure 6). conversion is initiated on the rising edge of convst . the falling edge of convst occurs 5.9 s later and can be used as either an active low or falling edge-triggered interrupt signal to tell the processor to read the data from the ad7890. provided the read operation is completed 500 ns before the rising edge of convst , the ad7890 will operate to specification. this scheme limits the throughput rate to 11.8 s minimum. how- ever, depending upon the response time of the microprocessor to the interrupt signal and the time taken by the processor to read the data, this may the fastest which the system could have operated. in any case, the convst signal does not have to have a 50:50 duty cycle. this can be tailored to optimize the throughput rate of the part for a given system. alternatively, the convst signal can be used as a normal nar- row pulsewidth. the rising edge of convst can be used as an active high or rising edge-triggered interrupt. a software delay of 5.9 s can then be implemented before data is read from the part. c ext functioning the c ext input on the ad7890 provides a means of determining how long after a new channel address is written to the part that a conversion can take place. the reason behind this is two-fold. firstly, when the input channel to the ad7890 is changed, the input voltage on this new channel is likely to be very different from the previous channel voltage. therefore, the parts track/ hold has to acquire the new voltage before an accurate con- version can take place. an internal pulse delays any conversion start command (as well as the signal to send the track/hold into hold) until after this pulse has timed out. the second reason is to allow the user to connect external antialiasing or signal conditioning circuitry between mux out and sha in. this external circuitry will introduce extra settling time into the system. the c ext pin provides a means for the user to extend the internal pulse to take this extra settling time into account. basically, varying the value of the capacitor on the c ext pin varies the duration of the internal pulse. figure 7 shows the relationship between the value of the c ext capaci- tor and the internal delay. c ext capacitance ?pf 0 internal pulsewidth ? s 64 56 48 40 32 24 16 8 0 250 500 750 1000 1250 1500 1750 2000 t a = ?0 c t a = +85 c t a = +25 c figure 7. internal pulsewidth vs. c ext rfs tfs t convert 500ns min convst sclk conversion is initiated and track/hold goes into hold conversion ends 5.9 s later serial read and write operations read and write operations should end 500ns prior to next rising edge of convst next convst rising edge p int service or polling routine figure 6. convst used as status signal in external clocking mode
rev. b ad7890 C13C the duration of the internal pulse can be seen on the c ext pin. the c ext pin goes from a low to a high when a serial write to the part is initiated (on the falling edge of tfs ). it starts to discharge on the sixth falling edge of sclk in the serial write operation. once the c ext pin has discharged to crossing its nominal trigger point of 2.5 v, the internal pulse is timed out. the internal pulse is initiated each time a write operation to the control register takes place. as a result, the pulse is initiated and the conversion process delayed for all software conver- sion start commands. for hardware conversion start, it is possible to separate the conversion start command from the internal pulse. if the multiplexer output (mux out) is connected directly to the track/hold input (sha in), then no external settling has to be taken into account by the internal pulsewidth. in applications where the multiplexer is switched and conversion is not initiated until more than 2 s after the channel is changed (as is possible with a hardware conversion start), the user does not have to worry about connecting any capacitance to the c ext pin. the 2 s equates to the track/hold acquisition time of the ad7890. in applications where the multiplexer is switched and conversion is initiated at the same time (such as with a software conversion start), a 120 pf capacitor should be connected to c ext to allow for the acquisition time of the track/hold before conversion is initiated. if external circuitry is connected between mux out and sha in, then the extra settling time introduced by this circuitry will have to be taken into account. in the case where the multiplexer change command and the conversion start command are separated, they need to be separated by greater than the acquisition time of the ad7890 plus the settling time of the external circuitry if the user does not have to worry about the c ext capacitance. in appli- cations where the multiplexer is switched and conversion is initiated at the same time (such as with a software conversion start), the capacitor on c ext needs to allow for the acquisition time of the track/hold plus the settling-time of the external circuitry before conversion is initiated. serial interface the ad7890s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers and digital signal processors. a serial read to the ad7890 accesses data from the output register via the data out line. a serial write to the ad7890 writes data to the control register via the data in line. two different modes of operation are available, optimized for different types of interface where the ad7890 can act either as master in the system (it provides the serial clock and data fram- ing signal) or acts as slave (an external serial clock and framing signal can be provided to the ad7890). these two modes, labelled self-clocking mode and external clocking mode, are discussed in detail in the following sections. self-clocking mode the ad7890 is configured for its self-clocking mode by tying the smode pin of the device to a logic low. in this mode, the ad7890 provides the serial clock signal and the serial data framing signal used for the transfer of data from the ad7890. this self-clocking mode can be used with processors which allow an external device to clock their serial port including most digital signal processors. read operation figure 8 shows a timing diagram for reading from the ad7890 in the self-clocking mode. at the end of conversion, rfs goes low and the serial clock (sclk) and serial data (data out) outputs become active. sixteen bits of data are transmitted with one leading zero, followed by the three address bits of the con- trol register, followed by the 12-bit conversion result starting with the msb. serial data is clocked out of the device on the rising edge of sclk and is valid on the falling edge of sclk. the rfs output remains low for the duration of the sixteen clock cycles. on the sixteenth rising edge of sclk, the rfs output is driven high and data out is disabled. rfs (o) sclk (o) data out (o) three-state t 1 t 3 t 2 t 4 t 5 t 6 t 7 three-state leading zero a2 a1 a0 db11 db10 db0 note: (i) signifies an input; (o) signifies an output. pull-up resistor on sclk. figure 8. self-clocking (master) mode output register read
rev. b ad7890 C14C write operation figure 9 shows a write operation to the control register of the ad7890. the tfs input is taken low to indicate to the part that a serial write is about to occur. tfs going low initiates the sclk output and this is used to clock data out of the proces- sors serial port and into the control register of the ad7890. the ad7890 control register requires only five bits of data. these are loaded on the first five clock cycles of the serial clock with data on all subsequent clock cycles being ignored. how- ever, the part requires six serial clock cycles to load data to the control register. serial data to be written to the ad7890 must be valid on the falling edge of sclk. external-clocking mode the ad7890 is configured for its external clocking mode by tying the smode pin of the device to a logic high. in this mode, sclk and rfs of the ad7890 are configured as inputs. this external-clocking mode is designed for direct interface to sys- tems which provide a serial clock output which is synchronized to the serial data output including microcontrollers such as the 80c51, 87c51, 68hc11 and 68hc05 and most digital signal processors. read operation figure 10 shows the timing diagram for reading from the ad7890 in the external-clocking mode. rfs goes low to access data from the ad7890. the serial clock input does not have to be continuous. the serial data can be accessed in a number of bytes. however, rfs must remain low for the duration of the data transfer operation. once again, sixteen bits of data are transmitted with one leading zero, followed by the three address bits in the control register, followed by the 12-bit conversion result starting with the msb. if rfs goes low during the high time of sclk, the leading zero is clocked out from the falling edge of rfs (as per figure 10). if rfs goes low during the low time of sclk, the leading zero is clocked out on the next rising edge of sclk. this ensures that, regardless of whether rfs goes low during a high time or low time of sclk, the leading zero is valid on the first falling edge of sclk after rfs goes low, provided t 14 and t 17 are adhered to. serial data is clocked out of the device on the rising edge of sclk and is valid on the falling edge of sclk. at the end of the read operation, the data out line is three-stated by a rising edge on either the sclk or rfs inputs, whichever occurs first. if a serial read from the output register is in progress when conversion is com- plete, the updating of the output register is deferred until the serial data read is complete and rfs returns high. write operation figure 11 shows a write operation to the control register of the ad7890. as with the self-clocking mode, the tfs input goes low to indicate to the part that a serial write is about to occur. as before, the ad7890 control register requires only five bits of data. these are loaded on the first five clock cycles of the serial clock with data on all subsequent clock cycles being ignored. how- ever, the part requires six serial clocks to load data to the control register. serial data to be written to the ad7890 must be valid on the falling edge of sclk. tfs (i) sclk (o) data in (i) t 4 t 8 a2 a1 a0 note: (i) signifies an input; (o) signifies an output. pull-up resistor on sclk. conv stby don t care don t care don t care t 3 t 9 t 10 t 11 t 12 figure 9. self-clocking (master) mode control register write rfs (i) sclk (i) data out (o) note: (i) signifies an input; (o) signifies an output. t 13 t 15 t 16 t 14 t 17 t 18 t 19 t 19a three-state leading zero a2 a1 a0 db11 db10 db0 figure 10. external clocking (slave) mode output register read
rev. b ad7890 C15C simplifying the interface to minimize the number of interconnect lines to the ad7890, the user can connect the rfs and tfs lines of the ad7890 together and read and write from the part simultaneously. in this case, new control register data should be provided on the data in line selecting the input channel and possibly providing a conversion start command while the part provides the result from the conversion just completed on the data out line. in the self-clocking mode, this means that the part provides all the signals for the serial interface. it does require that the micro- processor has the data to be written to the control register available in its output register when the part brings the tfs line low. in the external clocking mode, it means that the user only has to supply a single frame synchronization signal to control both the read and write operations. care must be taken with this scheme that the read operation is completed before the next conversion starts if the user wants to obtain optimum performance from the part. in the case of the software conversion start, the conversion command is written to the control register on the sixth serial clock edge. however, the read operation continues for another 10 serial clock cycles. to avoid reading during the sampling instant or during conversion, the user should ensure that the internal pulsewidth is sufficiently long (by choosing c ext ) so that the read operation is completed before the next conversion sequence begins. failure to do this will result in significantly degraded performance from the part, both in terms of signal-to-noise ratio and dc parameters. in the case of a hardware conversion start, the user should ensure that the delay between the sixth falling edge of the serial clock in the write operation and the next rising edge of convst is greater than the internal pulsewidth. microprocessor/microcontroller interface the ad7890s flexible serial interface allows for easy connec- tion to the serial ports of dsp processors and microcontrollers. figures 12 through 15 show the ad7890 interfaced to a num- ber of different microcontrollers and dsp processors. in some of the interfaces shown, the ad7890 is configured as the master in the system, providing the serial clock and frame sync for the read operation while in others it acts as a slave with these signals provided by the microprocessor. ad7890?051 interface figure 12 shows an interface between the ad7890 and the 8xc51 microcontroller. the ad7890 is configured for its exter- nal clocking mode while the 8xc51 is configured for its mode 0 serial interface mode. the diagram shown in figure 12 makes no provisions for monitoring when conversion is complete on the ad7890 (assuming hardware conversion start is used). to monitor the conversion time on the ad7890 a scheme such as outlined previously with convst can be used. this can be implemented in two ways. one is to connect the convst line to another parallel port bit which is configured as an input. this port bit can then be polled to determine when conversion is complete. an alternative is to use an interrupt driven system in which case the convst line should be connected to the int1 input of the 8xc51. since the 8xc51 contains only one serial data line, the data out and data in lines of the ad7890 must be connected together. this means that the 8xc51 cannot communicate with the output register and control register of the ad7890 at the same time. the 8xc51 outputs the lsb first in a write opera- tion so care should be taken in arranging the data which is to be transmitted to the ad7890. similarly, the ad7890 outputs the msb first during a read operation while the 8xc51 expects the lsb first. therefore, the data that is to be read into the serial port needs to be rearranged before the correct data word from the ad7890 is available in the microcontroller. the serial clock rate from the 8xc51 is limited to significantly less than the allowable input serial clock frequency with which the ad7890 can operate. as a result, the time to read data from the part will actually be longer than the conversion time of the part. this means that the ad7890 cannot run at its maximum throughput rate when used with the 8xc51. ad7890 v dd smode rfs tfs data out data in sclk 8xc51 p1.0 p1.1 p3.0 p3.1 figure 12. ad7890 to 8xc51 interface tfs (i) sclk (i) data in (i) a2 a1 a0 note: (i) signifies an input; (o) signifies an output. conv stby don t care don t care don t care t 20 t 21 t 22 t 23 figure 11. external clocking (slave) mode control register write
rev. b ad7890 C16C ad7890?8hc11 interface an interface circuit between the ad7890 and the 68hc11 microcontroller is shown in figure 13. for the interface shown, the ad7890 is configured for its external clocking mode while the 68hc11s spi port is used and the 68hc11 is configured in its single-chip mode. the 68hc11 is configured in the master mode with its cpol bit set to a logic zero and its cpha bit set to a logic one. as with the previous interface, there are no provisions for moni- toring when conversion is complete on the ad7890. to monitor the conversion time on the ad7890 a scheme, such as outlined in the previous interface with convst , can be used. this can be implemented in two ways. one is to connect the convst line to another parallel port bit which is configured as an input. this port bit can then be polled to determine when conversion is complete. an alternative is to use an interrupt driven system in which case the convst line should be connected to the irq input of the 68hc11. ad7890 dv dd smode rfs tfs data out data in sclk 68hc11 ss pc0 pc1 sck dv dd miso mosi figure 13. ad7890 to 68hc11 interface the serial clock rate from the 68hc11 is limited to significantly less than the allowable input serial clock frequency with which the ad7890 can operate. as a result, the time to read data from the part will actually be longer than the conversion time of the part. this means that the ad7890 cannot run at its maximum throughput rate when used with the 68hc11. ad7890?dsp-2101 interface an interface circuit between the ad7890 and the adsp-2101 dsp processor is shown in figure 14. the ad7890 is configured for its external clocking mode with the adsp-2101 providing the serial clock and frame synchronization signals. the rfs1 and tfs1 inputs and outputs are configured for active low operation. ad7890 dv dd smode rfs tfs data out data in sclk adsp-2101 rfs1 tfs1 sclk1 dr1 dt1 figure 14. ad7890 to adsp-2101 interface in the scheme shown, the maximum serial clock frequency the adsp-2101 can provide is 6.25 mhz. this allows the ad7890 to be operated at a sample rate of 111 khz. if it is desirable to operate the ad7890 at its maximum throughput rate of 117 khz, an external serial clock of 10 mhz can be provided to drive the serial clock input of both the ad7890 and the adsp-2101. to monitor the conversion time on the ad7890 a scheme, such as outlined in previous interfaces with convst , can be used. this can be implemented by connecting the convst line directly to the irq2 input of the adsp-2101. an alternative to this, where the user does not have to worry about monitoring the conversion status, is to operate the ad7890 in its self- clocking mode. in this scheme, the actual interface connections would remain the same as in figure 14 but now the ad7890 provides the serial clock and receive frame synchronization signals. using the ad7890 in its self-clocking mode limits the throughput rate of the system as the serial clock rate is limited to 2.5 mhz. ad7890?sp56000 interface figure 15 shows an interface circuit between the ad7890 and the dsp56000 dsp processor. the ad7890 is configured for its external clocking mode. the dsp56000 is configured for normal mode, synchronous operation with continuous clock. it is also set up for a 16-bit word with sck and sc2 as outputs. the fsl bit of the dsp56000 should be set to 0. the rfs and tfs inputs of the ad7890 are connected together so data is transmitted to and from the ad7890 at the same time. with the dsp56000 in synchronous mode, it provides a com- mon frame synchronization pulse for read and write operations on its sc2 output. this is inverted before being applied to the rfs and tfs inputs of the ad7890. to monitor the conversion time on the ad7890 a scheme, such as outlined in previous interface examples with convst , can be used. this can be implemented by connecting the convst line directly to the irqa input of the dsp56000. ad7890 dv dd smode rfs tfs data out data in sclk dsp56000 sc2 sck srd std figure 15. ad7890 to dsp56000 interface ad7890?ms320c25/30 interface figure 16 shows an interface circuit between the ad7890 and the tms320c25/30 dsp processor. the ad7890 is configured for its self-clocking mode where it provides the serial clock and frame synchronization signals. however, the tms320c25/30 requires a continuous serial clock. in the scheme outlined here, the ad7890s master clock signal, clk in, is used to provide the serial clock for the processor. the ad7890s output sclk, to which the serial data is referenced, is a delayed version of the clk in signal. the typical delay between the clk in and sclk is 20 ns and will be no more than 50 ns over supplies and tem- perature. therefore, there will still be sufficient setup time for
rev. b ad7890 C17C data out to be clocked into the dsp on the edges of the clk in signal. when writing data to the ad7890, the processors data hold time is sufficiently long to cater for the delay between the two clocks. the ad7890s rfs signal connects to both the fsx and fsr inputs of the processor. the processor can generate its own fsx signal so if required the interface can be modified so that the rfs and tfs signals are separated and the proces- sor generates the fsx signal which is connected to the tfs input of the ad7890. in the scheme outlined here, the user does not have to worry about monitoring the end of conversion. once conversion is complete, the ad7890 takes care of transmitting back its con- version result to the processor. once the sixteen bits of data have been received by the processor into its serial shift register, it generates an internal interrupt. since rfs and tfs are con- nected together, data is transmitted to the control register of the ad7890 whenever the ad7890 transmits its conversion result. the user just has to ensure that the word to be written to the ad7890 control register is set up prior to the end of con- version. as part of the interrupt routine, which recognizes that data has been read in, the processor can set up the data it is going to write to the control register next time around. ad7890 smode rfs tfs data out data in sclk tms320c25/c30 fsr fsx clkx clkr dr dx clk in clk input figure 16. ad7890 to tms320c25/30 interface antialiasing filter the ad7890 provides separate access to the multiplexer and adc via the mux out and sha in pins. one of the reasons for this is to allow the user to implement an antialiasing filter between the multiplexer and the adc. inserting the antialiasing filter at this point has the advantage that one antialiasing filter can suffice for all eight channels rather than a separate antialias- ing filter for each channel if they were to be placed prior to the multiplexer. the antialiasing filter inserted between the mux out and sha in pins will generally be a low-pass filter to remove high frequency signals which could possibly be aliased back in-band during the sampling process. it is recommended that this filter is an active filter, ideally with the mux out of the ad7890 driving a high impedance stage and the sha in of the part being driven from a low impedance stage. this will remove any effects from the variation of the parts multiplexer on-resistance with input signal voltage, and will also remove any effects of a high source impedance at the sampling input of the track/hold. with an external antialiasing filter in place, the additional set- tling time associated with the filter should be accounted for by using a larger capacitance on c ext . ad7890 performance linearity the linearity of the ad7890 is primarily determined by the on-chip 12-bit d/a converter. this is a segmented dac which is laser trimmed for 12-bit integral linearity and differential linearity. typical relative numbers for the part are 1/4 lsb while the typical dnl errors are 1/2 lsb. noise in an a/d converter, noise exhibits itself as code uncertainty in dc applications and as the noise floor (in an fft, for example) in ac applications. in a sampling a/d converter like the ad7890, all information about the analog input appears in the baseband from dc to 1/2 the sampling frequency. the input bandwidth of the track/hold exceeds the nyquist bandwidth and therefore an anti- aliasing filter should be used to remove unwanted signals above f s /2 in the input signal in applications where such signals exist. figure 17 shows a histogram plot for 8192 conversions of a dc input using the ad7890. the analog input was set at the centre of a code transition. the timing and control sequence used was as per figure 5 where the optimum performance of the adc was achieved. the same performance will be achieved in self- clocking mode where the part transmits its data after conversion is complete. it can be seen that almost all the codes appear in the one output bin indicating very good noise performance from the adc. the rms noise performance for the ad7890-2 for the above plot was 81 v. since the analog input range, and hence lsb size, on the ad7893-4 is 1.638 times what it is for the ad7893-2, the same output code distribution results in an out- put rms noise of 143 v for the ad7893-4. for the ad 7890-10, with an lsb size eight times that of the ad7890-2, the code distri- bution represents an output rms noise of 648 v. code occurrences of code 9000 (x 4) 8000 7000 6000 5000 4000 3000 2000 1000 0 (x 3) (x 2) (x 1) x (x+1) (x+2) (x+3) (x+4) sampling frequency = 102.4khz t a = 25 c figure 17. histogram of 8192 conversions of a dc input
rev. b ad7890 C18C in the external clocking mode, it is possible to write data to the control register or read data from the output register while a conversion is in progress. the same data is presented in figure 18 as in figure 17 except that in this case the output data read for the device occurs during conversion. these results are achieved with a serial clock rate of 2.5 mhz. if a higher serial clock rate is used, the code transition noise will degrade from that shown in the plot of figure 18. this has the effect of injecting noise onto the die while bit decisions are being made and this increases the noise generated by the ad7890. the histogram plot for 8192 conversions of the same dc input now shows a larger spread of codes with the rms noise for the ad7890-2 increasing to 170 v. this effect will vary depending on where the serial clock edges appear with respect to the bit trials of the conversion process. it is possible to achieve the same level of performance when reading during conversion as when reading after conversion depending on the relationship of the serial clock edges to the bit trial points (i.e., the relationship of the serial clock edges to the clk in edges). the bit decision points on the ad7890 are on the fall- ing edges of the master clock (clk in) during the conversion process. clocking out new data bits at these points (i.e., the rising edge of sclk) is the most critical from a noise standpoint. the most critical bit decisions are the msbs, so to achieve the level of performance outlined in figure 18, reading within 1 s after the rising edge of convst should be avoided. code occurrences of code (x 4) 8000 7000 6000 5000 4000 3000 2000 1000 0 (x 3) (x 2) (x 1) x (x+1) (x+2) (x+3) (x+4) sampling frequency = 102.4khz t a = 25 c figure 18. histogram of 8192 conversions with read during conversion writing data to the control register also has the effect of introduc- ing digital activity onto the part while conversion is in progress. however, since there are no output drivers active during a write operation, the amount of current flowing on the die is less than for a read operation. therefore, the amount of noise injected into the die is less than for a read operation. figure 19 shows the effect of a write operation during conversion. the histogram plot for 8192 conversions of the same dc input now shows a larger spread of codes than for ideal conditions but smaller than for a read operation. the resulting rms noise for the ad7890-2 is 110 v. in this case, the serial clock frequency was 10 mhz. code occurrences of code (x 4) 8000 7000 6000 5000 4000 3000 2000 1000 0 (x 3) (x 2) (x 1) x (x+1) (x+2) (x+3) (x+4) sampling frequency = 102.4khz t a = 25 c figure 19. histogram of 8192 conversions with write during conversion dynamic performance the ad7890 contains an on-chip track/hold, allowing the part to sample input signals up to 50 khz on any of its input chan- nels. many of the ad7890s applications will simply require it to sequence through low frequency input signals across its eight channels. there may be some applications, however, for which the dynamic performance of the converter out to 40 khz input frequency is of interest. it is recommended for these wider band sampling applications that the hardware conversion start method is used for reasons outlined previously. these applications require information on the adcs effect on the spectral content of the input signal. signal to (noise + distortion), total harmonic distortion, peak harmonic or spuri- ous and intermodulation distortion are all specified. figure 20 shows a typical fft plot of a 10 khz, 0 v to 2.5 v input after being digitized by the ad7890-2 operating at a 102.4 khz sam- pling rate. the signal to (noise + distortion) is 71.5 db and the total harmonic distortion is C85 db. it should be noted that reading data from the part during conversion at 10 mhz serial clock does have a significant impact on dynamic performance. for sampling applications, it is therefore recommended not to read data during conversion. frequency khz signal amplitude db 120 0 25.6 51.2 90 60 30 0 f = /2 sample rate = 102.4khz input frequency = 10khz snr = 71.5db t a = 25 c figure 20. ad7890 fft plot
rev. b ad7890 C19C input frequency khz 0 effective number of bits 12.0 11.5 11.0 10.5 10.0 20 40 '
#( !
'
, effective number of bits the formula for signal to (noise + distortion) ratio (see ter- minology section) is related to the resolution or number of bits in the converter. rewriting the formula, below, gives a measure of performance expressed in effective number of bits (n): n = (snr ? 1.76)/6.02 where snr is signal to (noise + distortion) ratio the effective number of bits for a device can be calculated from its measured signal to (noise + distortion) ratio. fig- ure 21 shows a typical plot of effective number of bits versus frequency for the ad7890-2 from dc to 40 khz. the sampling frequency is 102.4 khz. the plot shows that the ad7890 con- verts an input sine wave of 40 khz to an effective numbers of bits of 11 which equates to a signal to (noise + distortion) level of 68 db.
rev. b ad7890 C20C printed in u.s.a. c01357C0C2/01 (rev. b) outline dimensions dimensions shown in inches and (mm). plastic dip (n-24) 1.228 (31.19) 1.226 (31.14) 0.02 (0.5) 0.016 (0.41) 0.130 (3.30) 0.128 (3.25) 0.07 (1.78) 0.05 (1.27) seating plane 0.11 (2.79) 0.09 (2.28) pin 1 0.260 0.001 (6.61 0.03) 24 1 13 12 0.32 (8.128) 0.30 (7.62) 0.011 (0.28) 0.009 (0.23) 15 0 notes 1. lead no. 1 identified by dot or notch 2. plastic leads will be either solder dipped or tin plated in accordance with mil-m-38510 requirements. cerdip (q-24) pin 1 1 24 12 13 0.295 (7.493) max 0.225 (5.715) max 0.125 (3.175) min 0.070 (1.778) 0.020 (0.508) 0.180 (4.572) max 1.290 (32.77) max 0.021 (0.533) 0.015 (0.381) 0.065 (1.651) 0.055 (1.397) typ 0.110 (2.794) 0.090 (2.286) seating plane typ typ 0.320 (8.128) 0.290 (7.366) 15 0 0.012 (0.305) 0.008 (0.203) typ 1. lead no. 1 identified by dot or notch. 2. cerdip leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements. soic (r-24) 0.005 (1.27) 0.016 (0.40) 0.013 (0.32) 0.009 ( 0.23 ) 8 0 0.03 (0.75) 0.01 (0.25) pin 1 0.299 (7.6) 0.291 (7.39) 0.419 (10.65) 0.394 (10.00) 0.614 (15.6) 0.598 (15.2) 12 13 1 24 0.019 (0.49) 0.014 (0.35) 0.050 (1.27) 0.104 (2.65) 0.089 (2.35) 0.012 (0.3) 0.004 (0.1)
package/price information for detailed packaging information, please select the datasheets button. true bipolar input, single supply, 8-channel, 12-bit serial, data acquisition system ?model? status package description pin count temperature range price* (100-499) ?5962-9561501mla? ?production? ?cerdip glass seal? ?24? ?military? ?$83.16? ?ad7890achips-10? ?production? ?no conversion data from cos? - ?commercial? ?$12.00? ?AD7890ACHIPS-2? ?production? ?no conversion data from cos? - ?commercial? ?$12.00? ?ad7890an-10? ?production? ?plastic/epoxy dip? ?24? ?commercial? ?$12.00? ?ad7890an-2? ?production? ?plastic/epoxy dip? ?24? ?commercial? ?$12.00? ?ad7890an-4? ?production? ?plastic/epoxy dip? ?24? ?commercial? ?$12.00? ?ad7890ar-10? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? ?$12.00? ?ad7890ar-10reel? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? - ?ad7890ar-2? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? ?$12.00? ?ad7890ar-2reel? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? ?$12.00? ?ad7890ar-4? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? ?$12.00? ?ad7890ar-4reel? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? - ?ad7890bn-10? ?production? ?plastic/epoxy dip? ?24? ?commercial? ?$15.80? ?ad7890bn-2? ?production? ?plastic/epoxy dip? ?24? ?commercial? ?$15.80? ?ad7890bn-4? ?production? ?plastic/epoxy dip? ?24? ?commercial? ?$15.80? ?ad7890br-10? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? ?$15.80? ?ad7890br-10reel? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? - ?ad7890br-2? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? ?$15.80? ?ad7890br-2reel? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? ?$15.80? ?ad7890br-4? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? ?$15.80? ?ad7890br-4reel? ?production? ?std s.o. pkg (soic)? ?24? ?commercial? - ?ad7890sq-10? ?production? ?cerdip glass seal? ?24? ?commercial? ?$59.40? ?ad7890sq-2? ?production? ?cerdip glass seal? ?24? ?commercial? ?$59.40? analog products -- ad7890 file:///f|/cpl_new_images/ad7890.html (1 of 2) [7/17/2001 4:38:26 pm]
?ad7890sq-4? ?production? ?cerdip glass seal? ?24? ?commercial? ?$59.40? ?eval-ad7890-10eb? ?production? ?no conversion data from cos? - ?commercial? ?$150.00? ?eval-ad7890-2eb? ?production? ?no conversion data from cos? - ?commercial? ?$150.00? * this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability (currently available to north american customers) for further information. analog products -- ad7890 file:///f|/cpl_new_images/ad7890.html (2 of 2) [7/17/2001 4:38:26 pm]

▲Up To Search▲

Price & Availability of AD7890ACHIPS-2

	To Download AD7890ACHIPS-2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .